This invention relates to input-output interconnects and, more particularly, to integrated circuits with high-speed input-output interconnects.
Integrated circuits communicate with one another via communications pathways such as as input-output (I/O) buses. The Peripheral Component Interconnect Express® (commonly referred to as PCI Express or PCIe) technology is a widely adopted bus standard that provides high-speed serial point-to-point data transfer capabilities between integrated circuits. The PCIe interface is typically implemented using a layered architecture having a predefined protocol stack. The PCIe protocol stack includes a transaction layer, a data link layer, and a physical layer. Data that is being output via the PCIe interface and data that is being received via the PCIe interface are processed using the entire protocol stack.
A flow control module inside the transaction layer regulates the data transmission over a high-speed serial link based on available credits. The number of available credits is dependent on the number of available slots in a receive buffer in the transaction layer. Therefore, the number of available credits depends mostly on the size of the receive buffer and the speed at which data is read from the receive buffer.
Situations frequently arise where data transmission is stalled because fast-paced write operations, sometimes referred to as “posted write storms,” cause the receive buffer to fill up with data faster than the rate at which data can be processed by the application layer.